Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network

Abstract

Clock network design has become a great challenge since it accounts for a huge portion of chip power budget and and plays a crucial role determining circuit delay. Among different methods, clock mesh provides high robustness to process, voltage, and temperature (PVT) variations due to redundant paths. However, the mesh structure suffers from high power dissipation. By contrast, conventional clock tree structure is commonly used due to low power consumption, less routing resource usage. Nevertheless, a tree-based network is highly sensitive to PVT variations. In this paper, we propose to use the hybrid structure that combines tree-based and mesh-based structures for power and skew trade-off methodology. Experimental results suggest that hybrid-structured clock network can minimize the total capacitance under skew constrains.