Compact spin transfer torque non-volatile flip flop design for power-gating architecture

Abstract

This paper proposes a compact spin transfer torque non-volatile flip-flop (STT-NVFF) design. The proposed NVFF adds four transistors and two complementary magnetic tunnel junctions (MTJs) over a standard volatile flip-flop with only 18% area overhead. The NVFF utilizes a low power/ fast switching MTJ that permits the elimination of the write circuitry existing in conventional STT-NVFFs. The proposed NVFF is at least 80% smaller area than conventional STT-NVFFs that uses write circuitry with, at least, the same energy efficiency. It achieves a low backup energy of 111 fJ and restore energy of 6.9 fJ within 3 ns and 0.16 ns respectively. Moreover, it realizes a 72% reduction in break-even point (BEP) and a 10% area reduction compared to an STT-NVFF employing the latch as a writer.