Approach to 4-Core MPSoC Design Based on Matrix Computing

Abstract

The multi-core technique will play an important role in high density computing, therefore, it is significant to design MPSoC with handy intellectual property core. This paper gives the design of the 4-core multi-processor system on chip (MPSoC) based on hierarchy AHB bus architecture in RTL, and the testing results indicate that the speed increases along with the increasing dimension of the multiplication matrix. When the parallel program is beyond 95 percent in the total program, such as the 32 dimension matrix, the system speedup ratio is theoretically equal to the number of the cores integrated in MPSoC.