P. Fay, W. Li, L. Cao, K. Pourang, S. M. Islam, C. Lund, S. Saima, H. Ilatikhameneh, T. Amin, J. Huang, R. Rahman, D. Jena, S. Keller, Gerhard Klimeck
{"title":"Novel III-N heterostructure devices for low-power logic and more","authors":"P. Fay, W. Li, L. Cao, K. Pourang, S. M. Islam, C. Lund, S. Saima, H. Ilatikhameneh, T. Amin, J. Huang, R. Rahman, D. Jena, S. Keller, Gerhard Klimeck","doi":"10.1109/NANO.2016.7751336","DOIUrl":null,"url":null,"abstract":"Future ultra-scaled logic and low-power systems require fundamental advances in semiconductor device technology. Due to power constraints, device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if scaling of conventional computational architectures is to continue. Likewise, ultra low power systems also benefit from devices capable of maintaining performance under low-voltage operation. Towards this end, tunneling field effect transistors (TFETs) are one promising alternative. While much work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III-V materials, the use of III-N heterostructures and the exploitation of polarization engineering offers some unique opportunities. From physics-based simulations, performance of GaN/InGaN/GaN heterostructure TFETs appear capable of delivering average SS approaching 20 mV/decade over 4 decades of drain current, and on-current densities exceeding 100 μA/μm in aggressively scaled nanowire configurations. Experimental progress towards realizing III-N based TFETs includes demonstration of GaN/InGaN/GaN backward tunnel diodes by both MOCVD and MBE, and nanowires grown selectively by MBE and used as the basis for device fabrication.","PeriodicalId":6646,"journal":{"name":"2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)","volume":"4 1","pages":"767-769"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 16th International Conference on Nanotechnology (IEEE-NANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NANO.2016.7751336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Future ultra-scaled logic and low-power systems require fundamental advances in semiconductor device technology. Due to power constraints, device concepts capable of achieving switching slopes (SS) steeper than 60 mV/decade are essential if scaling of conventional computational architectures is to continue. Likewise, ultra low power systems also benefit from devices capable of maintaining performance under low-voltage operation. Towards this end, tunneling field effect transistors (TFETs) are one promising alternative. While much work has been devoted to realizing TFETs in Si, Ge, and narrow-gap III-V materials, the use of III-N heterostructures and the exploitation of polarization engineering offers some unique opportunities. From physics-based simulations, performance of GaN/InGaN/GaN heterostructure TFETs appear capable of delivering average SS approaching 20 mV/decade over 4 decades of drain current, and on-current densities exceeding 100 μA/μm in aggressively scaled nanowire configurations. Experimental progress towards realizing III-N based TFETs includes demonstration of GaN/InGaN/GaN backward tunnel diodes by both MOCVD and MBE, and nanowires grown selectively by MBE and used as the basis for device fabrication.