A 3bit/cell 32Gb NAND flash memory at 34nm with 6MB/s program throughput and with dynamic 2b/cell blocks configuration mode for a program throughput increase up to 13MB/s

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI:10.1109/ISSCC.2010.5433949

G. Marotta, A. Macerola, A. D'Alessandro, A. Torsi, C. Cerafogli, C. Lattaro, C. Musilli, Doyle Rivers, E. Sirizotti, F. Paolini, Giuliano Gennaro Imondi, G. Naso, G. Santin, L. Botticchio, L. D. Santis, L. Pilolli, M. Gallese, M. Incarnati, M. Tiburzi, P. Conenna, S. Perugini, V. Moschiano, W. D. Francesco, M. Goldman, C. Haid, D. D. Cicco, D. Orlandi, F. Rori, M. Rossini, T. Vali, R. Ghodsi, Frankie Roohparvar

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引用次数: 44

Abstract

In recent years applications such as mp3 players, SSD, digital cameras and video camcorders have driven the development of increasingly higher density NAND memories. In the presented 3b/cell memory the read and programming throughputs are been enhanced with the adoption of a quad-plane architecture and an industry standard even-odd bitline (BL) decoding scheme. The architecture, while featuring same page size of 16KB as recently disclosed ABL architectures [3,4], avoids the shortcomings such an ABL scheme exhibits in programming mode due to floating-gate-to-floating-gate coupling. The chip features both the newly developed synchronous DDR interface and the standard, asynchronous NAND flash interface. A 66-cell string is adopted to optimize the die size at 126mm2.

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3bit/cell 32Gb的34nm NAND闪存，具有6MB/s的程序吞吐量，采用动态2b/cell块配置模式，可将程序吞吐量提高到13MB/s

近年来，mp3播放器、固态硬盘、数码相机和摄像机等应用推动了高密度NAND存储器的发展。在所提出的3b/cell存储器中，通过采用四平面结构和行业标准的奇偶位线(BL)解码方案，提高了读取和编程吞吐量。该体系结构与最近披露的ABL体系结构[3,4]具有相同的16KB页面大小，避免了ABL方案在编程模式中由于浮动门到浮动门耦合而出现的缺点。该芯片具有新开发的同步DDR接口和标准的异步NAND闪存接口。采用66单元串优化126mm2的芯片尺寸。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2010 IEEE International Solid-State Circuits Conference - (ISSCC)

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