A Subharmonic CMOS Mixer Based on Threshold Voltage Modulation

Abstract

A novel CMOS subharmonic mixing technique based on threshold voltage modulation with higher LO-to-RF isolation is presented in this paper. A 2.1GHz subharmonic mixer is designed using this technique in a 0.18µm standard digital CMOS process by applying the LO signals at the bulk terminal of PMOS transistors. The mixer has a measured conversion gain of 10.5dB, an IIP3 of −3.5dBm, and a noise figure of 17.7dB while consuming 2.5mW in each mixer core. This circuit architecture increases the second harmonic LO-to-RF isolation to above 67dB and hence can mitigate LO leakage issues in wireless receivers.