An 182mW 1-60Gb/s Configurable PAM-4/NRZ Transceiver for Large Scale ASIC Integration in 7nm FinFET Technology

2022 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2022-02-20 DOI:10.1109/ISSCC42614.2022.9731688

N. Kocaman, U. Singh, Bharath Raghavan, Arvindh Lyer, Kumar Thasari, Saurabh Surana, Jun Won Jung, J. Jeong, Heng Zhang, Anand Vasani, Y. Shim, Z. Huang, A. Garg, Hsiang-bin Lee, Bo Wu, Feifei Liu, Ray Wang, Matthew Loh, Alex Wang, M. Caresosa, Bo Zhang, A. Momtaz

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引用次数: 3

Abstract

With the COVID–19 pandemic, the faster and more reliable connectivity solutions in data centers became the critical enabler technology of our daily activities. The current 50G data center switches have more than 500 lanes within a single chip solution [1]. This massive integration puts strict restrictions on power/area consumption. Moreover, single-domain, low supply voltage operation is highly desirable for better package/board designs as well as improved silicon reliability with less aging impact. An ADC-based receiver with DSP equalization consumes higher power/area due to the time-interleaved ADC array and digital domain FFE/DFE taps [2]. An analog CTLE/DFE-based transceiver with a single supply level is highly suitable for low power/area operation for high density IOs in data center switches. The TX driver supply level can be adjusted based on the application.

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用于7nm FinFET技术的大规模ASIC集成的182mW 1-60Gb/s可配置PAM-4/NRZ收发器

随着COVID-19大流行，数据中心更快、更可靠的连接解决方案成为我们日常活动的关键使能技术。目前的50G数据中心交换机在单芯片解决方案中有超过500个通道[1]。这种大规模集成严格限制了功耗/面积消耗。此外，单域、低电源电压操作对于更好的封装/电路板设计以及提高硅可靠性和减少老化影响是非常理想的。由于时间交错ADC阵列和数字域FFE/DFE抽头，带有DSP均衡的基于ADC的接收器消耗更高的功率/面积[2]。基于模拟CTLE/ dfe的单电源收发器非常适合数据中心交换机中高密度io的低功耗/区域操作。TX驱动供电电平可以根据应用进行调整。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 IEEE International Solid- State Circuits Conference (ISSCC)

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