Designing of Modified Area Efficient Square Root Carry Select Adder (SQRT CSLA)

Abstract

In the design of Integrated Circuits, The necessity of portable systems is increasing an area occupancy plays a vital role. Square Root Carry Select Adder (SQRT CSLA) is one of the fastest adders which is used in this data-processing processor to perform fast arithmetic functions. In this paper, an area-efficient square root carry select adder(SQRT CSLA design) by sharing Common Boolean logic term (CBL) is proposed The modified architecture has been developed using Binary to Excess-1 converter (BEC). Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed by using CBl. The proposed design has reduced area as well as power,but in this we study only for area with a slight increase in the delay.