Self-super-cutoff power gating with state retention on a 0.3V 0.29fJ/cycle/gate 32b RISC core in 0.13µm CMOS

Abstract

Using ultra low-voltage (ULV) is a viable approach towards lowering power consumption. However, due to the narrowing gap between the supply voltage and the threshold voltage, ULV designs inevitably suffer from either low performance or high leakage [1, 2]. Specifically, for applications that demand performance, low-threshold devices must be used and so leakage remains a significant problem. The most effective approach to cutting down leakage is power gating. In this regard, the SCCMOS [3] (Fig. 24.4.1, left) uses additional boost signals to “super cutoff” the leakage current. In SCCMOS, a charge pump is used to generate the boost signal, and the pump has to be on during the standby period to maintain the boost signal. As such, the leakage saved by the super cutoff may be far less than that consumed by the charge pump, negating the power advantages of ULV SCCMOS.