Y. Ohtomo, T. Mizusawa, K. Nishimura, H. Sawada, M. Ino
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引用次数: 4
Abstract
A quarter-micron SIMOX-CMOS gate array with an LVTTL interface is described. The SIMOX-CMOS gates have the same delay at 1.2 V of supply voltage as that of the gates in 0.5-/spl mu/m bulk CMOS at 3.3 V and reduce power consumption 87%. The interface circuits in the array convert 3.3 V external signal from/to 2.0 V-1.2 V internal signal with little power penalty. An ESD protection circuit for the chip shows over 2,000 V of ESD hardness in the advanced SIMOX-CMOS having 50-nm thick silicon film.