High-performance reduced-size 70–80 GHz CMOS branch-line hybrid using CPW and CPWG guided-wave structures

Abstract

A folding technique is proposed to reduce the size of CPW based branch-line couplers without compromising their electrical characteristics. The technique is used to fabricate a high-performance 90° 70–80 GHz hybrid coupler in 130-nm CMOS with a 35% layout area reduction. Grounded coplanar waveguide (CPWG) based structures are used for the low impedance lines while complying with the CMOS metal spacing and width layout rules. Experimental measurements across the bandwidth show a maximum insertion loss of 1.4 dB, an amplitude imbalance less than 0.6 dB, a phase imbalance less than 2°, and an input return loss greater than 19.5 dB. The coupler footprint is 0.203 mm2.