Seongjong Kim, Inyong Kwon, D. Fick, Myungbo Kim, Yen-Po Chen, D. Sylvester
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引用次数: 58
Abstract
Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These variations cause performance uncertainty for which timing margins must be added to guarantee correct operation. Ultimately, this results in lost performance or energy: performance is lost directly through reduced clock frequency, while energy is sacrificed by operating at a higher voltage than necessary to meet non-margined timing requirements.