3D power grid modeling

Abstract

The paper describes on-chip 3D power grid (PG) modeling for high performance CPU designs. We show that for high frequencies (above 1 GHz) it is necessary to use the full RLM PG model with extracted partial self and mutual conductors' inductances, rather than resistive R or RL models. We also present a practical model reduction technique named "real space reduction" (RSR), which enables simplifying the model and reduces memory and simulation time without significant accuracy losses.