Synchronizing Sequences For Verification Of Finite State Machines

Abstract

The method of detection and localization of design errors in HDL-models of finite state machines with arbitrary output functions was proposed. The diagnostic experiment is carried out bypassing all arcs of the Mealy machine, starting from the initial vertex, including for machines of the "non-exclusive" class. To ensure the return of the machine with a possible design error in the initial state, it is suggested to use synchronizing sequences. Diagnostic experiments were performed in the Active-HDL design environment.