A HARDWARE ACCELERATOR FOR THE COMPUTATION OF MODIFIED DISCRETE SINE TRANSFORM

Abstract

This work presents an efficient hardware implementation of a hardware accelerator for the computation of the Modified Discrete Sine transform (MDST) using a new VLSI algorithm based on a appropriate reformulation of the MDST algorithm using some auxiliary input and output sequences. The obtained hardware implementation is using a low complexity implementation based on only adders/subtracters and has a reduced critical path that can be exploited to obtain a significant reduction of the power consumption.