Design of faster & power efficient sense amplifier using VLSI technology

Abstract

In this paper we have designed Faster & Power Efficient Sense Amplifier for CMOS SRAM using VLSI Technology i.e. primarily schematic of sense amplifier is designed & simulated using ADS (Advanced Design System). The sense amplifier then implemented & analyzed at chip level using Microwind 3.1- a layout editor. The 45 nm & 32 nm technologies are used to analyze performance of Sense Amplifier. Our focus will be to reduce the size, to improve the power consumption and also to improve the response time of sense amplifier.