Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno
{"title":"Study of C2W Bonding Using Cu Pillar with Side-Wall Plated Solder","authors":"Ling Xie, S. Wickramanayaka, V. N. Sekhar, Daniel Ismael Cereno","doi":"10.1109/ECTC.2017.260","DOIUrl":null,"url":null,"abstract":"Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.","PeriodicalId":6557,"journal":{"name":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","volume":"1 1","pages":"1572-1577"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE 67th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2017.260","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Cu-Cu is a prefer choice of interconnects as it offered lower electrical resistance, no risk of shorting between the bump and higher reliability as compared to Cu-Solder Bump. However, Cu-Cu interconnect requests stringent condition such as Cu bump surface topography, flatness, uniformity of pillar array heights and clean bonding surface. From throughput point of view, Cu-Cu bonding is challenging as bonding profile involves long heating duration and high temperature. In this paper, we explore the method to improve the bonding throughput and improve interconnect formation. A novel Cu pillar structure is proposed with center core Cu pillar surrounded by side-wall layer solder. Such Cu pillar array is bonded on a bottom wafer with Cu pads through chip-to-wafer (C2W) method. Study shows the solder located at side-wall offers an assist of temporary tacking the chip on the wafer. Then the entire interconnect forms joint through the use of gang bonder. As the side-wall solder seals individual Cu pillar to corresponding bond pad, it helps to prevent non-contact or void interconnection in pillar array. With the tacking and gang bonding process, a higher throughput process can be realized and actively adopted by industry as it offers lower cost of assembly.