Power Optimized Comparator Selecting Method For Stochastic ADC

Abstract

This work presents a power saving design method for stochastic flash analog-to-digital converters (ADCs). Stochastic ADCs use the offset noise distribution generated by mismatch to estimate the input signal. By analyzing the characteristic of the noise distribution, some of comparator cells in the stochastic ADC are unused for a given input range. The proposed comparator selection method allows the unused comparators to be powered down without affecting performance of the ADC. A behavioral model of the stochastic ADC is used to simulate and compare the power consumption of the ADC with and without the proposed technique.