{"title":"How to derive a quantum complexity lower bound","authors":"Tetsuro Nishino","doi":"10.1002/ecjc.20298","DOIUrl":null,"url":null,"abstract":"<p>The modeling of computation using logic circuits occupies an important position in the fundamentals of complexity theory including quantum complexity theory. Consequently, research into methods for computing logic functions on quantum circuits as well as for minimizing and simplifying such circuits has become extremely important. In this paper we explicitly formulate the depth minimization problem for quantum logic circuits and show that this problem is closely related to a geometric approach to deriving a lower bound on the size of a quantum logic circuit. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(10): 9–17, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20298</p>","PeriodicalId":100407,"journal":{"name":"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)","volume":"90 10","pages":"9-17"},"PeriodicalIF":0.0000,"publicationDate":"2007-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1002/ecjc.20298","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Electronics and Communications in Japan (Part III: Fundamental Electronic Science)","FirstCategoryId":"1085","ListUrlMain":"https://onlinelibrary.wiley.com/doi/10.1002/ecjc.20298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The modeling of computation using logic circuits occupies an important position in the fundamentals of complexity theory including quantum complexity theory. Consequently, research into methods for computing logic functions on quantum circuits as well as for minimizing and simplifying such circuits has become extremely important. In this paper we explicitly formulate the depth minimization problem for quantum logic circuits and show that this problem is closely related to a geometric approach to deriving a lower bound on the size of a quantum logic circuit. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 90(10): 9–17, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.20298
如何导出量子复杂度下界
使用逻辑电路的计算建模在包括量子复杂度理论在内的复杂度理论基础中占有重要地位。因此,对计算量子电路上的逻辑函数以及最小化和简化这种电路的方法的研究变得极其重要。在本文中,我们明确地公式化了量子逻辑电路的深度最小化问题,并表明这个问题与导出量子逻辑电路大小下界的几何方法密切相关。©2007 Wiley Periodicals,股份有限公司Electron Comm Jpn Pt 3,90(10):2007年9月17日;在线发表于Wiley InterScience(www.InterScience.Wiley.com)。DOI 10.1002/ecjc.20298
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