{"title":"GD80—A multi-microprocessor architecture for computer graphics","authors":"P Verebély","doi":"10.1016/0303-1268(80)90089-9","DOIUrl":null,"url":null,"abstract":"<div><p>GD80 is a modular family of refresh, vector-type graphic displays. Five microprocessors for different tasks communicate on two separate busses using interprocessors interrupts, memory windows and shared memory with hardware supported mutual exclusion. Two identical 8 bit microprocessors are dedicated for peripheral handling and communication, two 16 bit microprogrammable bit-slice processors for picture generation and display list processing, and a 48 bit one for fast floating point arithmetic calculations and matrix-vector transformations. This paper describes the main building blocks, the multiprocessing methods and some typical configurations built using the modules.</p></div>","PeriodicalId":100495,"journal":{"name":"Euromicro Newsletter","volume":"6 6","pages":"Pages 406-409"},"PeriodicalIF":0.0000,"publicationDate":"1980-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/0303-1268(80)90089-9","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Euromicro Newsletter","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/0303126880900899","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
GD80 is a modular family of refresh, vector-type graphic displays. Five microprocessors for different tasks communicate on two separate busses using interprocessors interrupts, memory windows and shared memory with hardware supported mutual exclusion. Two identical 8 bit microprocessors are dedicated for peripheral handling and communication, two 16 bit microprogrammable bit-slice processors for picture generation and display list processing, and a 48 bit one for fast floating point arithmetic calculations and matrix-vector transformations. This paper describes the main building blocks, the multiprocessing methods and some typical configurations built using the modules.