A Capacitance Model for Front- and Back-Gate Threshold Voltage Computation of Ultra-Thin-Body and BOX Double-Insulating Silicon-on-Diamond MOSFET

Abstract

In this paper, a capacitance model for near threshold voltage computation of Ultra-Thin-Body and BOX (UTBB) Double-Insulating (DI) Silicon-on-Diamond (SOD) MOSFET is proposed. The transistor has a second insulating layer on top of the first insulating layer of a conventional SOD MOSFET which partially covers the diamond layer. The device’s simulation results of the front- and back-gate threshold voltages and the computed model’s threshold voltages - in terms of gate oxide thickness, silicon film layer thickness, first and second insulating layer thicknesses - are compared. In addition, length of the source/drain overlap with the second insulating layer is varied and the device simulation results are compared with those of the model findings. Results of the aforesaid comparison are found to be promising; more than 20 mV change in front-gate threshold voltage is observed at the range of 5 nm to 43 nm. Moreover, the model is found to be applicable in computations of front- and back-gate threshold voltage of 22 nm DI UTBB SOD MOSFET for low drain voltages. Finally, the model’s physical findings present insight on the device’s parameters that directly influence the threshold voltage