Optimized vedic multiplier using low power 13T hybrid full adder

IF 1.1 Q3 INFORMATION SCIENCE & LIBRARY SCIENCE
Mansi Jhamb, M. Kumar
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引用次数: 0

Abstract

The research paper detects a modified version of the Vedic multiplier by using the sutras of Vedic mathematics by implementing a 13T hybrid full adder. A conventional multiplier is considered for comparative analysis of existing Vedic versions and a modified Vedic multiplier that better reflects the timing and usage of the device. This technology was developed and implemented by EDA. The proposed 13T hybrid full adder is achieved to reduce the static power consumption by 12.12 % and dynamic power consumption by 15.7%. The modified Vedic multiplier is implemented by using a 13T hybrid full adder which is achieved to reduce the power consumption by 10.08% and delay by 2.068%. The circuit and simulation are executed for 4-bit multiplication and can be performed in Eight-bit, Sixteen-bit or Thirty-two-bit. Results of simulation are shown only in the Vedic 4-bit multiplication technique. The results of this multiplication method are compared with existing techniques of Vedic multiplicative circuits.
优化的吠陀乘法器采用低功耗13T混合全加法器
研究论文通过使用吠陀数学经典,通过实现13T混合全加法器,检测了吠陀乘数的修改版本。传统的倍增器被考虑用于比较分析现有的吠陀版本和改进的吠陀倍增器,后者更好地反映了装置的时间和使用。该技术是由EDA开发和实现的。实现了13T混合全加法器,静态功耗降低12.12%,动态功耗降低15.7%。改进的韦达乘法器采用13T混合全加法器实现,功耗降低10.08%,时延降低2.068%。电路和仿真可用于4位乘法,也可用于8位、16位或32位乘法。仿真结果仅显示在Vedic 4位乘法技术中。该乘法方法的结果与现有的吠陀乘法电路技术进行了比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
JOURNAL OF INFORMATION & OPTIMIZATION SCIENCES
JOURNAL OF INFORMATION & OPTIMIZATION SCIENCES INFORMATION SCIENCE & LIBRARY SCIENCE-
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21.40%
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88
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