A 0.6-V 41.3-GHz Power-Scalable Sub-Sampling PLL in 55-nm CMOS DDC

IF 0.6 4区工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC

IEICE Transactions on Electronics Pub Date : 2023-01-01 DOI:10.1587/transele.2022cts0001

Sangyeop Lee, K. Takano, S. Amakawa, T. Yoshida, M. Fujishima

引用次数: 0

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基于55nm CMOS DDC的0.6 v 41.3 ghz功率可扩展子采样锁相环

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEICE Transactions on Electronics 工程技术-工程：电子与电气

CiteScore

1.00

自引率

20.00%

发文量

审稿时长

3-6 weeks

期刊介绍： Currently, the IEICE has ten sections nationwide. Each section operates under the leadership of a section chief, four section secretaries and about 20 section councilors. Sections host lecture meetings, seminars and industrial tours, and carry out other activities. Topics: Integrated Circuits, Semiconductor Materials and Devices, Quantum Electronics, Opto-Electronics, Superconductive Electronics, Electronic Displays, Microwave and Millimeter Wave Technologies, Vacuum and Beam Technologies, Recording and Memory Technologies, Electromagnetic Theory.