Polyhedral-Based Compilation Framework for In-Memory Neural Network Accelerators

IF 2.1 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Jianhui Han, Xiang Fei, Zhaolin Li, Youhui Zhang
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引用次数: 1

Abstract

Memristor-based processing-in-memory architecture is a promising solution to the memory bottleneck in the neural network ( NN ) processing. A major challenge for the programmability of such architectures is the automatic compilation of high-level NN workloads, from various operators to the memristor-based hardware that may provide programming interfaces with different granularities. This article proposes a source-to-source compilation framework for such memristor-based NN accelerators, which can conduct automatic detection and mapping of multiple NN operators based on the flexible and rich representation capability of the polyhedral model. In contrast to previous studies, it implements support for pipeline generation to exploit the parallelism in the NN loads to leverage hardware resources for higher efficiency. The evaluation based on synthetic kernels and NN benchmarks demonstrates that the proposed framework can reliably detect and map the target operators. Case studies on typical memristor-based architectures also show its generality over various architectural designs. The evaluation further demonstrates that compared with existing polyhedral-based compilation frameworks that do not support the pipelined execution, the performance can upgrade by an order of magnitude with the pipelined execution, which emphasizes the necessity of our improvement.
基于多面体的内存神经网络加速器编译框架
基于忆阻器的内存处理架构是解决神经网络处理中内存瓶颈的一种很有前途的方法。这种架构的可编程性面临的一个主要挑战是高级神经网络工作负载的自动编译,从各种操作符到可能提供不同粒度编程接口的基于忆阻器的硬件。本文提出了一种基于记忆电阻器的神经网络加速器的源到源编译框架,该框架利用多面体模型灵活丰富的表示能力,对多个神经网络算子进行自动检测和映射。与以往的研究相比,它实现了对管道生成的支持,以利用神经网络负载的并行性来利用硬件资源以提高效率。基于合成核和神经网络基准的评估表明,该框架能够可靠地检测和映射目标算子。对典型的基于忆阻器的体系结构的案例研究也表明了它在各种体系结构设计中的通用性。评估进一步表明,与现有的不支持流水线执行的基于多面体的编译框架相比,流水线执行的性能可以提升一个数量级,从而强调了我们改进的必要性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems 工程技术-工程:电子与电气
CiteScore
4.80
自引率
4.50%
发文量
86
审稿时长
3 months
期刊介绍: The Journal of Emerging Technologies in Computing Systems invites submissions of original technical papers describing research and development in emerging technologies in computing systems. Major economic and technical challenges are expected to impede the continued scaling of semiconductor devices. This has resulted in the search for alternate mechanical, biological/biochemical, nanoscale electronic, asynchronous and quantum computing and sensor technologies. As the underlying nanotechnologies continue to evolve in the labs of chemists, physicists, and biologists, it has become imperative for computer scientists and engineers to translate the potential of the basic building blocks (analogous to the transistor) emerging from these labs into information systems. Their design will face multiple challenges ranging from the inherent (un)reliability due to the self-assembly nature of the fabrication processes for nanotechnologies, from the complexity due to the sheer volume of nanodevices that will have to be integrated for complex functionality, and from the need to integrate these new nanotechnologies with silicon devices in the same system. The journal provides comprehensive coverage of innovative work in the specification, design analysis, simulation, verification, testing, and evaluation of computing systems constructed out of emerging technologies and advanced semiconductors
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