A Simple and Fast Solution for Fault Simulation Using Approximate Parallel Critical Path Tracing

Abstract

Due to the growing complexity of today’s digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of complex circuits with a large number of faults and tests. Exact stem analysis is the most important obstacle in accelerating the CPT method. The simplification of stem analysis eliminates time-consuming computations and makes the CPT method more parallelizable. An approximate and bit-parallel CPT algorithm is proposed for ultrafast fault simulation for both stuck-at-fault (SAF) and transition delay fault (TDF) models. Time linearity, speedup, and accuracy of the proposed algorithm are examined and evaluated using ISCAS85, ISCAS89, and ITC99 benchmark circuits. In order to assess the accuracy, the false-positive and false-negative detection of faults are counted for each benchmark circuit. The experimental results reveal considerable speedup as well as acceptable accuracy of the proposed approach in comparison with the traditional methods and commercial fault simulators.