Secure and Energy Efficient Design of Multi-Modular Exponential Techniques for Public-Key Cryptosystem

Utkarsh Tiwari;Satyanarayana Vollala;N. Ramasubramanian;B. Sameedha Begum;G. Lakshminarayanan
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Abstract

The present paper proposes a secure design of the energy-efficient multi-modular exponential techniques that use store and reward method and store and forward method. Computation of the multi-modular exponentiation can be performed by three novel algorithms: store and reward, store and forward 1-bit (SFW1), and store and forward 2-bit (SFW2). Hardware realizations of the proposed algorithms are analyzed in terms of throughput and energy. The experimental results show the proposed algorithms SFW1 and SFW2 increase the throughput by orders of 3.98% and 4.82%, reducing the power by 5.32% and 6.15% and saving the energy in the order of 3.95% and 4.75%, respectively. The proposed techniques can prevent possible side-channel attacks and timing attacks as a consequence of an inbuilt confusion mechanism. Xilinx Vivado-21 on Virtex-7 evaluation board and integrated computer application for recognizing user services (ICARUS) Verilog simulation and synthesis tools are used for field programmable gate array (FPGA) for hardware realization. The hardware compatibility of proposed algorithms has also been checked using Cadence for application specific integrated circuit (ASIC).
公钥密码系统的多模指数技术安全节能设计
本文提出了一种采用存储奖励法和存储转发法的节能多模指数技术的安全设计方法。多模幂的计算可以通过三种新颖的算法来完成:存储和奖励、存储和转发1位(SFW1)和存储和转发2位(SFW2)。从吞吐量和能量两方面分析了所提算法的硬件实现。实验结果表明,本文提出的算法SFW1和SFW2分别提高了3.98%和4.82%的吞吐量,降低了5.32%和6.15%的功耗,节约了3.95%和4.75%的能量。所提出的技术可以防止可能的侧信道攻击和定时攻击作为一个内置的混淆机制的结果。Xilinx Vivado-21基于Virtex-7评估板和集成计算机应用程序识别用户服务(ICARUS) Verilog仿真和合成工具用于现场可编程门阵列(FPGA)的硬件实现。所提出的算法的硬件兼容性也使用Cadence用于特定应用集成电路(ASIC)进行了检查。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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