An Analytical Gate Delay Variability Model for Low-Power Applications under the Process Variations Effects

Abstract

Defining the timing characteristics behavior, such as the gate delay and the oscillation period, is an essential task in integrated circuits (ICs), especially for low-power CMOS-based technologies. The nanometric-sized devices designed to achieve low-power consumption have higher threshold voltages. Hence, these devices are operated at the near-threshold regime, or slightly above the threshold. In these regions, shifts in electrical parameters (expressed in terms of drain current or threshold voltage) may severely impact the circuit behavior. Consequently, the time-dependent sources of variability (e.g., the bias temperature instability) impose a crucial reliability problem that affects time delay variability and induces slope propagation effects along the signal path. In this context, an improved analytical model to properly account for both the gate delay and its variability is presented, taking into account the properties of low-power devices. Additionally, the applicability of the model is presented in a case study of a ring oscillator. The derived equations allows a suitable estimative for the parameters’ degradation. Supported by Monte Carlo simulations, the extracted results indicate that the proposed method provides a better estimate for the ring oscillator jitter when compared to the simplified propagation of uncertainty method.