TCI Tester: A Chip Tester for Inductive Coupling Wireless Through-Chip Interface

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Journal of Low Power Electronics and Applications Pub Date : 2023-08-04 DOI:10.3390/jlpea13030048

Hideto Kayashima, H. Amano

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Abstract

The building block computation system is constructed by stacking various chips three-dimensionally. The stacked chips incorporate the same TCI IP (Through Chip Interface Intellectual Property) but cannot provide identical characteristics, requiring adjustments in power supply and bias voltage. However, providing characteristics measurement hardware for all chips is difficult due to the limitation of chip area or pin numbers. To address this problem, we developed TCI Tester, a small chip to measure electric characteristics by stacking on TCI of every chip. By stacking two TCI Tester chips, it appears that the up-directional data transfer has a stricter condition than down directional one on power supply voltage and operational frequency. Also, the transfer performance is poorer than designed. Similar measurement results are obtained by stacking TCI Tester on other chips with TCI IP. To investigate the reason, we analyzed the power grid resistance of various chips with the TCI IP. Results also showed that the chips with higher resistance have a narrow operational condition and poorer performance. The results suggest that the power grid design is important for keeping the performance through the TCI channel.

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TCI测试仪：一种用于电感耦合无线芯片接口的芯片测试仪

构建块计算系统是通过三维堆叠各种芯片来构建的。堆叠芯片包含相同的TCI IP（芯片接口知识产权），但不能提供相同的特性，需要调整电源和偏置电压。然而，由于芯片面积或引脚数量的限制，为所有芯片提供特性测量硬件是困难的。为了解决这个问题，我们开发了TCI测试仪，这是一种通过堆叠在每个芯片的TCI上来测量电气特性的小型芯片。通过堆叠两个TCI测试器芯片，在电源电压和工作频率方面，上行数据传输比下行数据传输具有更严格的条件。此外，传输性能比设计的差。通过将TCI测试器堆叠在具有TCI IP的其他芯片上，获得了类似的测量结果。为了研究原因，我们分析了TCI IP芯片的电网电阻。结果还表明，电阻越高的芯片工作条件越窄，性能越差。结果表明，电网设计对于保持TCI通道的性能至关重要。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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