Extreme Path Delay Estimation of Critical Paths in Within-Die Process Fluctuations Using Multi-Parameter Distributions

IF 1.6 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Miikka Runolinna, M. Turnquist, Jukka Teittinen, Pauliina Ilmonen, L. Koskinen
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引用次数: 1

Abstract

Two multi-parameter distributions, namely the Pearson type IV and metalog distributions, are discussed and suggested as alternatives to the normal distribution for modelling path delay data that determines the maximum clock frequency (FMAX) of a microprocessor or other digital circuit. These distributions outperform the normal distribution in goodness-of-fit statistics for simulated path delay data derived from a fabricated microcontroller, with the six-term metalog distribution offering the best fit. Furthermore, 99.7% confidence intervals are calculated for some extreme quantiles on each dataset using the previous distributions. Considering the six-term metalog distribution estimates as the golden standard, the relative errors in single paths vary between 4 and 14% for the normal distribution. Finally, the within-die (WID) variation maximum critical path delay distribution for multiple critical paths is derived under the assumption of independence between the paths. Its density function is then used to compute different maximum delays for varying numbers of critical paths, assuming each path has one of the previous distributions with the metalog estimates as the golden standard. For 100 paths, the relative errors are at most 14% for the normal distribution. With 1000 and 10,000 paths, the corresponding errors extend up to 16 and 19%, respectively.
基于多参数分布的模内过程波动临界路径的极端路径延迟估计
讨论并提出了两种多参数分布,即Pearson IV型分布和metalog分布,作为对确定微处理器或其他数字电路的最大时钟频率(FMAX)的路径延迟数据建模的正态分布的替代方案。对于从制造的微控制器导出的模拟路径延迟数据,这些分布在拟合优度统计方面优于正态分布,六项metalog分布提供了最佳拟合。此外,使用先前的分布为每个数据集上的一些极端分位数计算了99.7%的置信区间。考虑到六项metalog分布估计作为黄金标准,正态分布的单路径相对误差在4%到14%之间变化。最后,在路径独立的假设下,推导了多条关键路径的模内变化最大关键路径延迟分布。然后,它的密度函数用于计算不同数量的关键路径的不同最大延迟,假设每条路径都有一个以前的分布,以metalog估计为黄金标准。对于100条路径,正态分布的相对误差最多为14%。对于1000和10000条路径,相应的误差分别扩展到16%和19%。
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来源期刊
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications Engineering-Electrical and Electronic Engineering
CiteScore
3.60
自引率
14.30%
发文量
57
审稿时长
11 weeks
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