Vertically-stacked silicon nanosheet field effect transistors at 3 nm technology nodes - simulation at nanoscale

Abstract

Feasibility of vertically-stacked silicon nanosheet FETs (SNS-FETs) for extreme scaling at 3 nm technology node are investigated for the first time as one of the possible solutions to continue to enhance the performances of the CMOS technology. In this work, we use 3D predictive simulations to study the performance potential of SNS-FETs at 3 nm technology node. With the end of happy scaling era, change of device architecture has raised integration complexity along with severe short channel effects, mobility degradation, variability and quantum tunnelling leakage. These are the major challenges as device dimensions are scaled for ultimate scaling below 7 nm. Towards low power and high speed (more-than-Moore applications), nanowires and nanosheet transistors are being proposed. Today, the possibility of FinFET downscaling is still open and more than ever alternatives to CMOS transistors, such as, vertically-stacked SNS-FETs are showing their potential to surpass FinFETs. Variability due to metal grain granularity (MGG) is critical at 3 nm technology nodes, as such, the device threshold voltage variation due to MGG is examined for single nanosheet NS-FET. Finally, we calculate the mean and standard deviation of these parameters to quantify the variability.