Validation of Proposed Test Set Reduction Hybrid Compaction Schemes for FPGA-Based Designs

A. R. Khatri
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引用次数: 0

Abstract

Recently, the density and intricacy of Very Large-Scale Integration (VLSI) circuits are grown, and the number of test vectors has increased drastically. Owing to this, the cost of testing is a significant component for consideration. The two main factors that measure the cost of the test are the size of the test vector sets and test data volume. Compression and compaction are the two approaches used to reduce the aforementioned factors. Compaction is a primary process in the test generation procedure, and there are two classes for it, i.e., dynamic and static compaction approaches. In this paper, the author performs testing and obtains the compact test vectors for various FPGA-based designs. The RASP-FIT fault injection testing tool provides the ATPG testing framework. In this paper, the testing is performed on various FPGA benchmark designs written in Verilog HDL, and the results are validated. The ATPG method developed under the RASP-FIT tool contains new hybrid compaction techniques that calculate compaction and fault coverage for the designs. This work is also compared with the previous work and found that the proposed compaction scheme is better at compacting the test vectors.
基于FPGA设计的测试集缩减混合压缩方案的验证
近年来,超大规模集成电路的密度和复杂性不断增加,测试矢量的数量急剧增加。因此,测试成本是一个需要考虑的重要组成部分。衡量测试成本的两个主要因素是测试向量集的大小和测试数据量。压缩和压实是用于减少上述因素的两种方法。压实是测试生成过程中的一个主要过程,有两类,即动态压实和静态压实方法。在本文中,作者对各种基于FPGA的设计进行了测试并获得了紧凑的测试向量。RASP-FIT故障注入测试工具提供了ATPG测试框架。本文对用Verilog HDL编写的各种FPGA基准设计进行了测试,并对结果进行了验证。在RASP-FIT工具下开发的ATPG方法包含新的混合压实技术,用于计算设计的压实度和故障覆盖率。该工作还与以前的工作进行了比较,发现所提出的压实方案在压实测试向量方面更好。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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