Guest Editors Introduction: Special Issue on Network-on-Chip Architectures of the Future (NoCArc)

Abstract

© 1 h s the number of cores integrated into the same integrated circuit increases, the role of the etwork-on-Chip (NoC)—as the communication infrastructure—becomes increasingly more imortant. Next-generation many-core processor systems continue to face communication-related calability problems, which are further exacerbated by ultra-deep sub-micron effects induced by he next silicon technology nodes. The emergence of novel computing paradigms consisting of ccelerators, quantum computing, DNA computing storage technologies, and optical computing an have deep and far-reaching implications on the future of interconnects. Integration platforms uch as interposers and processing-in-memory are also predicted to influence the course of NoC esearch. Furthermore, applications such as big data, artificial intelligence, deep learning, and cyersecurity will also impact the future of NoC research. With the end of Dennard scaling, large many-core processor systems are disaggregated into maller chiplets or dielets and are integrated using traditional platforms such as boards as well s emerging technologies such as 2.5D interposers, Silicon Photonics (SiPh), or wireless interonnects. Interposers are large silicon dies with minimum or no active devices providing abunant wiring resources to interconnect dielets integrated on sockets in the interposer. The capabilty to reuse older more mature technology nodes due to minimum active devices and the use of nly long-distance global wire-based interconnects make interposers a natural choice for low-cost nd sustainable scalable platforms that do not need new materials and can reuse existing fabriation nodes. The abundant wiring resources provide new opportunities for scaling the number f chiplets in the system and for research into novel, application-informed Network-in-Package NiP) designs that provide designers a wide range of tradeoffs in performance, energy efficiency, eliability, scalability, and sustainability. SiPh is maturing as an on-chip and chip-to-chip interconnect technology. Using miniature ring esonators, Mach-Zehnder modulator/demodulators, and waveguides, dense wavelength division ultiplexing is supported where multiple pairs of senders and receivers can communicate with igh bandwidth over chip-side dimensions with ultra-low latency and improved energy efficiency. ntegration and miniaturization of the SiPh devices at larger densities and elimination of electroptic domain conversions remain open challenges in this field. Wireless and radio frequency communication among cores in a many-core system over NoC or iP links can provide latency-bound communication using miniature millimeter-wave or sub-THz ands over multi-gigabit per second links. Wireless communication provides support for broadcast r multicast traffic, which is extremely beneficial in many-core processor systems due to essential ontrol messages such as cache coherency protocol messages. By eliminating repeated unicasts,