Simulation-based evaluation of bit-interaction side-channel leakage on RISC-V: extended version

IF 1.5 4区计算机科学 Q2 COMPUTER SCIENCE, THEORY & METHODS

Journal of Cryptographic Engineering Pub Date : 2023-06-20 DOI:10.1007/s13389-023-00319-z

Tamon Asano, T. Sugawara

引用次数: 0

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基于RISC-V的位交互侧信道泄漏仿真评估:扩展版

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Journal of Cryptographic Engineering COMPUTER SCIENCE, THEORY & METHODS-

CiteScore

4.70

自引率

0.00%

发文量

期刊介绍： The Journal of Cryptographic Engineering (JCEN) presents high-quality scientific research on architectures, algorithms, techniques, tools, implementations and applications in cryptographic engineering, including cryptographic hardware, cryptographic embedded systems, side-channel attacks and countermeasures, and embedded security. JCEN serves the academic and corporate R&D community interested in cryptographic hardware and embedded security.JCEN publishes essential research on broad and varied topics including:Public-key cryptography, secret-key cryptography and post-quantum cryptographyCryptographic implementations include cryptographic processors, physical unclonable functions, true and deterministic random number generators, efficient software and hardware architecturesAttacks on implementations and their countermeasures, such as side-channel attacks, fault attacks, hardware tampering and reverse engineering techniquesSecurity evaluation of real-world cryptographic systems, formal methods and verification tools for secure embedded design that offer provable security, and metrics for measuring securityApplications of state-of-the-art cryptography, such as IoTs, RFIDs, IP protection, cyber-physical systems composed of analog and digital components, automotive security and trusted computing