A Simple Stuck-at-faults Detection Method in Digital Combinational Circuits

Abstract

This paper considers the new method of detection (diagnostic) stuck-at-faults (0/1) in digital combinational circuits based on a numerical set-theoretical approach. Compared to known methods and algorithms, the proposed approach differs in simpler implementation of searching for vectors of test codes at arbitrary points of the studied logic circuit. A few simple set-theoretical operations and procedures are sufficient to determine the location and the type of a stuck-at-fault (0/1). This is evidenced by the presented examples of application of the proposed method, that are borrowed from the publications of well-known authors.