Second Generation of Layout Styles to Further Boosting the Electrical Performance and Reducing the Die Area of Analog MOSFETs

Abstract

Previous studies have been showing that the first generation of layout styles composed by the Diamond (hexagonal), Octo (octagonal) and Ellipsoidal gate shapes for implementing of the planar and three-dimensional MOSFETs are is capable of boosting their analog and digital electrical performances and also by reducing used die areas, when we replace conventional Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), that present rectangular gate shape, by those implemented by these innovative layout styles. In order to further boosting these features obtained by the use of first generation of layout styles, we are introducing one of elements of the second generation of layout styles for MOSFETs, intitled Half-Diamond. This new proposal is an evolution of Diamond layout style, in which it is able to preserve the Longitudinal Corner Effect (LCE), the Parallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivation of Parasitic MOSFETs in Bird’s Beaks Regions (DEMPAMBBRE) effects of the first generation and also of further reducing the dimensions of conventional MOSFETs (CM) in which the Diamond MOSFETs have gotten to do. Thus, this work performs an experimental comparative study between the electric performances of MOSFETs implemented with the Half-Diamond, Diamond and Conventional layout styles, regarding the analog Complementary MOS (CMOS) integrated circuits (ICs) applications, which their channel lengths are not usually designed with the minimum dimension (Lmin) allowed by the CMOS ICs manufacturing processes. The results obtained show that, for instance, the saturation drain current normalized by the aspect ratio and low-frequency open-loop voltage gain, in dB, of MOSFET implemented with the Half-Diamond layout style (HDM) are 17% and 3.5% higher, respectively, than those found in CM counterparts. Besides, by using Half-Diamond layout style, it is possible of further reducing the die areas of analog CM and consequently of the analog CMOS ICs applications, in comparison to those reached by the use of  Diamond layout styles, regarding a 180 nm Bulk CMOS ICs technology node.