Optimization of a Moore Automaton Circuit in a Mixed Element Basis

Abstract

Introduction. The control unit is one of the most important building blocks of any digital system. The main function of the control unit is to coordinate the interaction between all system blocks. Therefore, the characteristics of a control unit circuit have a significant impact on the quality of the system as a whole. To represent the law of functioning of a control unit, the models of the Moore and Mealy finite state machines (FSM) are used. When synthesizing circuits of FSMs, it is necessary to solve a number of optimization problems, such as the reducing hardware amount, increasing performance, minimizing power consumption, joint optimization of hardware-temporal characteristics. Methods for solving these problems largely depend on the used logical elements. Currently, FPGA microchips are one of the main platforms in which modern digital systems are implemented. The main blocks in the FPGA, which are used in the implementation of FSM circuits, are embedded memory blocks (EMBs), logical blocks LUT (look-up table) and a system of programmable interconnections. The best characteristics are possessed by FSM circuits implemented with EMBs. However, EMBs are widely used to implement various operational blocks of digital systems. Therefore, the designer of a control unit circuitry can use a rather limited number of EMBs. Purpose of the article. The article deals with the extreme case when there is only a single "free" EMB available. In this case, the FSM circuit is represented by a network consisting of this EMB and LUTs. There is proposed a method for the synthesis of an FSM with the optimization of the number of LUTs, when only one EMB block is available for implementing some part of the circuit. The proposed method is based on the using classes of pseudoequivalent states of Moore FSMs. The states are coded in such a way that the state code consists of the code of the class of pseudoequivalent states and the code of a collection of microoperations. Results. Studies of the effectiveness of the proposed method were carried out on standard FSMs. FPGAs of the Virtex-7 family from Xilinx were used as an implementation platform. The research results showed that the proposed method allows reducing the number of LUTs in FSM circuits by 12 % – 19 % in comparison with the known methods. In all cases, only a single EMB was used. Conclusions. The effectiveness of the proposed method allows us to recommend it for use in the synthesis of FSMs if there is of an extreme shortage of EMBs. Keywords: Moore FSM, FPGA, LUT, EMB, pseudoequivalent states, synthesis.