A Unified Power-Delay Model for GDI Library Cell Created Using New Mux Based Signal Connectivity Algorithm

Q1 Multidisciplinary
Jebashini Ponnian, Senthil Pari, U. Ramadass, Chee Pun Ooi
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Abstract

The challenges of innovative IC technology typically come with various new design constraints in terms of circuit implementation, behaviour, scaling, and an accurate power-delay model to evaluate the circuit's performance. The circuit realization technique using GDI is gaining popularity because of its power and transistor utilization factors. Considering the core advantage of the GDI technique, this research presents the creation of new GDI library cells implemented using the MUX-based algorithm and its delay-power model. This research defines two goals; the former goal depicts the proposal of GDI library cells with full swing using a MUX-based signal connectivity model, and the later presents the mathematical delay-power model for the proposed GDI library cells. The number of attributes defined in the delay and power model incorporates minimum variables without sacrificing precision. It calculates the delay for simple RC networks and combinational circuits with multiple paths. The power model is given using the node activity factor and the power factor related to the internal node capacitances, wiring, and gate capacitances of the driving and receiving GDI nodes. The experimental results of this study, which conform to the specifications of the sub-micron library supported for the SilTerra 130 nm 6-metal layer fabricated for the CMOS n-well process, demonstrate that the proposed GDI library is indeed superior in terms of delay-transistor and power utilisation to PTL and CMOS technology. The simulation results reveal that there is 55 to 65 % improvement in terms of power and delay factor with the existing CMOS and PTL logic. The proposed delay model demonstrates that GDI cells require less logical effort than CMOS technology. The proposed power model shows that the node activity factor of the proposed GDI cells lies between 0.1 and 0.2, while in CMOS, it is between 0.1 and 0.3. Doi: 10.28991/ESJ-2023-07-04-022 Full Text: PDF
基于多路复用的信号连接新算法建立了GDI库单元的统一功率延迟模型
创新IC技术的挑战通常伴随着电路实现、行为、缩放和评估电路性能的精确功率延迟模型方面的各种新设计约束。使用GDI的电路实现技术由于其功率和晶体管利用因素而越来越受欢迎。考虑到GDI技术的核心优势,本研究提出了使用基于MUX的算法及其延迟功率模型来创建新的GDI库单元。本研究定义了两个目标;前一个目标描述了使用基于MUX的信号连通性模型全面提出GDI库单元,而后者提出了所提出的GDI库单元格的数学延迟功率模型。在不牺牲精度的情况下,延迟和功率模型中定义的属性数量包含最小变量。它计算了简单RC网络和具有多路径的组合电路的延迟。使用节点活动因子和与驱动和接收GDI节点的内部节点电容、布线和栅极电容相关的功率因子来给出功率模型。本研究的实验结果符合为CMOS n阱工艺制造的SilTerra 130nm 6金属层所支持的亚微米库的规范,表明所提出的GDI库在延迟晶体管和功率利用方面确实优于PTL和CMOS技术。仿真结果表明,与现有的CMOS和PTL逻辑相比,在功率和延迟因子方面有55%到65%的改进。所提出的延迟模型表明,GDI单元比CMOS技术需要更少的逻辑工作。所提出的功率模型表明,所提出的GDI单元的节点活动因子在0.1和0.2之间,而在CMOS中,它在0.1和0.3之间。Doi:10.28991/ESJ-2023-07-004-022全文:PDF
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Emerging Science Journal
Emerging Science Journal Multidisciplinary-Multidisciplinary
CiteScore
5.40
自引率
0.00%
发文量
155
审稿时长
10 weeks
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