A Novel Technique for Minimization of March Test Using Read Equivalent Stress

Abstract

Static random access memory is popularly used in the cache memories due to its infinite and very fast read/write operations. As technology advances, size of devices shrinks and the percent of manufacturing defects in integrated circuits increases significantly which results in different types of faults. The most crucial part regarding testing is achieving maximum fault coverage with minimal test time. March SR+ is one of the test used frequently in the industry, which has a higher percentage of fault detection with a test length of 18N. In this paper, we propose a novel technique to minimise the test time of March SR+. On this basis, we introduce a more efficient alternative to March SR+. The reformulation of March SR+ is essentially based on introducing a particular addressing sequence and read/write data sequence. This modification does not alter the capability of March SR+ to detect the former target faults, but extends the ability of many conventional March-based test solutions in detecting dynamic read destructive faults without any test modification. Moreover, fault detection using the proposed methodology results in a significant reduction of 11.1% in test time and 11.04% in average power consumption.