Quenching Circuit Discriminator Architecture Impact on a Sub-10 ps FWHM Single-Photon Timing Resolution SPAD

Abstract

In the field of radiation instrumentation, there is a desire to reach a sub-10 ps FWHM timing resolution for applications such as time-of-flight positron emission tomography, time-of-flight positron computed tomography and time-resolved calorimetry. One of the key parts of the detection chain for these applications is a single-photon detector and, in recent years, the first single-photon avalanche diode (SPAD) with a sub-10 ps timing resolution was presented. To reach such a timing resolution, the SPAD was read out by an operational amplifier operated in open-loop as a comparator. This paper presents a comparison between comparators and inverters to determine which type of leading-edge discriminator can obtain the best single-photon timing resolution. Six different quenching circuits (QCs) implemented in TSMC 65 nm are tested with SPADs of the same architecture and in the same operation conditions. This allows us to compare experimental results between the different QCs. This paper also presents a method to measure the SPAD signal slope, the SPAD excess voltage variation and simulations to determine the added jitter of different leading-edge discriminators. For some discriminator architectures, a cascode transistor was required to increase the maximum excess voltage of the QC. This paper also presents the impact on the single-photon timing resolution of adding a cascode transistor for a comparator or an inverter-based discriminator. This paper reports a 6.3 ps FWHM SPTR for a SPAD read out by a low-threshold comparator and a 6.8 ps FWHM SPTR for an optimized 1 V inverter using a cascode transistor for a higher excess voltage.