Area, delay and power comparison of fault-tolerant systems with TMR using different voter circuits

Abstract

In a current very large-scale integration (VLSI) technology evolution, the reliability issues are the major concern for the improvement of the system. The most fundamental method used for the fault-tolerant system is triple modular redundancy (TMR) in which the majority voter circuit is used to obtain the fault-free response. In this study, the different voter circuits are implemented to analyse the least layout area and lower power dissipation with an application-specific integrated circuits (ASIC) approach using the Microwind layout editor tool. This work is carried out with the eight voting circuits including two proposed methods. The application examples such as a 32-bit adder, an unsigned 8×8 array multiplier, bitwise XOR operation and a 3 × 3 high-pass filter are demonstrated to compare the performance of different voters. The simulation results (power, area, delay) for all the four application examples are obtained and compared.