Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation

IF 2.8 4区 计算机科学 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Stylianos I. Venieris, J. Fernández-Marqués, Nicholas D. Lane
{"title":"Mitigating Memory Wall Effects in CNN Engines with On-the-Fly Weights Generation","authors":"Stylianos I. Venieris, J. Fernández-Marqués, Nicholas D. Lane","doi":"10.1145/3611673","DOIUrl":null,"url":null,"abstract":"The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high-performance and energy-efficient inference, significant research effort has been invested in the design of FPGA-based CNN accelerators. In this context, single computation engines constitute a popular design approach that enables the deployment of diverse models without the overhead of fabric reconfiguration. Nevertheless, this flexibility often comes with significantly degraded performance on memory-bound layers and resource underutilisation due to the suboptimal mapping of certain layers on the engine’s fixed configuration. In this work, we investigate the implications in terms of CNN engine design for a class of models that introduce a pre-convolution stage to decompress the weights at run time. We refer to these approaches as on-the-fly. This paper presents unzipFPGA, a novel CNN inference system that counteracts the limitations of existing CNN engines. The proposed framework comprises a novel CNN hardware architecture that introduces a weights generator module that enables the on-chip on-the-fly generation of weights, alleviating the negative impact of limited bandwidth on memory-bound layers. We further enhance unzipFPGA with an automated hardware-aware methodology that tailors the weights generation mechanism to the target CNN-device pair, leading to an improved accuracy-performance balance. Finally, we introduce an input selective processing element (PE) design that balances the load between PEs in suboptimally mapped layers. Quantitative evaluation shows that the proposed framework yields hardware designs that achieve an average of 2.57 × performance efficiency gain over highly optimised GPU designs for the same power constraints and up to 3.94 × higher performance density over a diverse range of state-of-the-art FPGA-based CNN accelerators.","PeriodicalId":50944,"journal":{"name":"ACM Transactions on Design Automation of Electronic Systems","volume":" ","pages":""},"PeriodicalIF":2.8000,"publicationDate":"2023-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM Transactions on Design Automation of Electronic Systems","FirstCategoryId":"94","ListUrlMain":"https://doi.org/10.1145/3611673","RegionNum":4,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0

Abstract

The unprecedented accuracy of convolutional neural networks (CNNs) across a broad range of AI tasks has led to their widespread deployment in mobile and embedded settings. In a pursuit for high-performance and energy-efficient inference, significant research effort has been invested in the design of FPGA-based CNN accelerators. In this context, single computation engines constitute a popular design approach that enables the deployment of diverse models without the overhead of fabric reconfiguration. Nevertheless, this flexibility often comes with significantly degraded performance on memory-bound layers and resource underutilisation due to the suboptimal mapping of certain layers on the engine’s fixed configuration. In this work, we investigate the implications in terms of CNN engine design for a class of models that introduce a pre-convolution stage to decompress the weights at run time. We refer to these approaches as on-the-fly. This paper presents unzipFPGA, a novel CNN inference system that counteracts the limitations of existing CNN engines. The proposed framework comprises a novel CNN hardware architecture that introduces a weights generator module that enables the on-chip on-the-fly generation of weights, alleviating the negative impact of limited bandwidth on memory-bound layers. We further enhance unzipFPGA with an automated hardware-aware methodology that tailors the weights generation mechanism to the target CNN-device pair, leading to an improved accuracy-performance balance. Finally, we introduce an input selective processing element (PE) design that balances the load between PEs in suboptimally mapped layers. Quantitative evaluation shows that the proposed framework yields hardware designs that achieve an average of 2.57 × performance efficiency gain over highly optimised GPU designs for the same power constraints and up to 3.94 × higher performance density over a diverse range of state-of-the-art FPGA-based CNN accelerators.
利用飞行重量生成减轻CNN引擎中的记忆壁效应
卷积神经网络(CNNs)在广泛的人工智能任务中具有前所未有的准确性,导致其在移动和嵌入式环境中得到广泛部署。为了追求高性能和节能的推理,在基于FPGA的CNN加速器的设计上投入了大量的研究工作。在这种情况下,单个计算引擎构成了一种流行的设计方法,它能够在没有结构重新配置开销的情况下部署不同的模型。然而,这种灵活性往往伴随着内存绑定层的性能显著下降,以及由于引擎固定配置上某些层的次优映射而导致的资源利用不足。在这项工作中,我们研究了CNN引擎设计对一类模型的影响,该模型引入了预卷积阶段来在运行时解压缩权重。我们将这些方法称为动态方法。本文提出了一种新的CNN推理系统unzip FPGA,它克服了现有CNN引擎的局限性。所提出的框架包括一种新颖的CNN硬件架构,该架构引入了一个权重生成器模块,该模块能够在芯片上动态生成权重,减轻有限带宽对内存绑定层的负面影响。我们通过一种自动化的硬件感知方法进一步增强了unzip FPGA,该方法根据目标CNN设备对定制权重生成机制,从而提高了精度和性能的平衡。最后,我们介绍了一种输入选择性处理元件(PE)设计,该设计在次优映射层中平衡PE之间的负载。定量评估表明,在相同的功率约束下,所提出的框架产生的硬件设计比高度优化的GPU设计平均实现2.57倍的性能效率增益,在各种最先进的基于FPGA的CNN加速器上实现高达3.94倍的性能密度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems 工程技术-计算机:软件工程
CiteScore
3.20
自引率
7.10%
发文量
105
审稿时长
3 months
期刊介绍: TODAES is a premier ACM journal in design and automation of electronic systems. It publishes innovative work documenting significant research and development advances on the specification, design, analysis, simulation, testing, and evaluation of electronic systems, emphasizing a computer science/engineering orientation. Both theoretical analysis and practical solutions are welcome.
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