A low power high speed single phase clock level restoring 16T master-slave flip-flop

IF 0.8 4区 工程技术 Q4 ENGINEERING, ELECTRICAL & ELECTRONIC
Alok Mishra, Urvashi Chopra, Vaithiyanathan D., B. Kaur
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引用次数: 0

Abstract

Purpose A low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops. Design/methodology/approach This paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops. Findings The proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop. Originality/value This work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.
一种低功耗高速单相时钟电平恢复16T主从触发器
目的低功耗触发器电路是为节能器件设计的。数字时序电路的需求量很大,因为每个处理器都有数字电路的大部分部件。时序电路由一个基本数据存储元件组成,一个锁存器用于存储单比特数据。触发器占据了总芯片面积和总功耗的足够部分。这项研究的目标是低功耗节能应用,如笔记本电脑、手机和掌上电脑。设计/方法/方法本文提出了一种新型触发器,它只由16个晶体管和单相时钟组成。触发器有两个块,主锁存器和从锁存器。在这个设计中,作者只关注主锁存器,它包括一个电平恢复电路。它用于帮助主锁存数据保留过程。锁存电路具有背靠背布置的两个反相器。所提出的触发器在65上实现 nm互补金属氧化物半导体技术,使用Cadence Virtuoso环境,并与其他报道的触发器进行比较。结果所提出的触发器架构优于峰值百分比,即与传输门触发器相比为79.25%,与18相比最低为20.02% T真正的单相时钟(TSPC)在功率方面的改进。它还改进了C到Q延迟和功率延迟乘积。此外,通过减少晶体管的数量,相对于18TSPC和现有触发器,所提出的触发器的总面积至少减少了13.76%。为了进行可靠性检查,对1000个样本进行了蒙特卡罗模拟,并将其与最近报道的18TSPC触发器进行了比较。原始性/值通过使用负载电容器为0.2的测试电路来测试这项工作 所提出的工作使用了一种新的拓扑结构作为主从式工作。这种技术的功耗非常低,最适合低功耗应用。此电路工作正常,最高可达2 GHz频率。
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来源期刊
Circuit World
Circuit World 工程技术-材料科学:综合
CiteScore
2.60
自引率
0.00%
发文量
33
审稿时长
>12 weeks
期刊介绍: Circuit World is a platform for state of the art, technical papers and editorials in the areas of electronics circuit, component, assembly, and product design, manufacture, test, and use, including quality, reliability and safety. The journal comprises the multidisciplinary study of the various theories, methodologies, technologies, processes and applications relating to todays and future electronics. Circuit World provides a comprehensive and authoritative information source for research, application and current awareness purposes. Circuit World covers a broad range of topics, including: • Circuit theory, design methodology, analysis and simulation • Digital, analog, microwave and optoelectronic integrated circuits • Semiconductors, passives, connectors and sensors • Electronic packaging of components, assemblies and products • PCB design technologies and processes (controlled impedance, high-speed PCBs, laminates and lamination, laser processes and drilling, moulded interconnect devices, multilayer boards, optical PCBs, single- and double-sided boards, soldering and solderable finishes) • Design for X (including manufacturability, quality, reliability, maintainability, sustainment, safety, reuse, disposal) • Internet of Things (IoT).
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