Fast Hardware Implementation of AES-128 Algorithm in Streaming Output Feedback Mode for Real Time Ciphering

Abstract

Information security is one of the main challenges faced today in purview of the increase in trend of online purchases. Many ciphering schemes are available that provide data encryption. But the strength of stream ciphers available is very squat as compared to block ciphers. To ensure better security, block ciphers are used in various ways for streaming application at the cost of increased computational load. This paper discusses the implementation of AES-128 in output feedback (OFB) mode for real-time streaming applications. The target performance parameter for the implementation of the algorithm is speed as well as reduced memory resources. Implementation techniques for various blocks of the algorithm have been discussed for achieving the target performance. The implementation is functionally tested on Virtex – 6 FPGA. The performance achieved in terms of latency, speed, memory resources and other logic resources is also presented. This shows the effectiveness of the proposed hardware implementation for real-time streaming cipher applications.