Electro‐Thermal Analysis of a Double‐Gate Vertical Tunnel Field‐Effect Transistor Under Multiple Power‐Dissipation Regimes

Abstract

Tunnel field‐effect transistors (TFETs) complement MOSFETs in low‐power electronics through steep switching. This work analyses a double‐gate vertical TFET (DG‐VTFET) under realistic electro‐thermal coupling, capturing the combined influence of temperature and power dissipation. At 300 K the device delivers an OFF‐current near 10 − 1 5 A, an ON‐current of about 6 × 10 − 5 A/µm, and an average subthreshold swing (SS) of 11.8 mV/dec. Under high‐power operation the global device temperature reaches approximately 430 K, degrading mobility, ON‐current and transconductance. A 10 × 10 array simulated at low‐, medium‐ and high‐power dissipation shows marked degradation of SS, radio‐frequency (RF) response and linearity, the temperature influence being nonuniform across bias. The diffusive lattice heat‐flow description is validated rather than assumed at the 10 nm body thickness: size‐dependent thermal conductivity from the phonon Boltzmann transport equation (BTE) is verified against a direct Monte Carlo BTE solution of the full Si/Ge stack. This correction raises the peak temperature by 3.7 K in DC and 2.6 K in AC operation, bounded above by 5 K, so reported temperatures are lower bounds and the conclusions unchanged, the buried oxide dominating the thermal resistance of this vertical architecture. Electro‐thermal coupling is therefore essential for reliable nanoscale TFET design.