A low-latency 163-bit ECC processor for IoT applications

Abstract

Abstract Extensive research is being carried out on elliptic curve cryptography and its applications in resource-constrained environments such as IoT. Yet, critical gaps, such as high computational overhead in ECC operations, scalar multiplication and computationally expensive inversion, remain unanswered. Existing ECC implementations focus on improving either multiplication or inversion separately, but an integrated, optimized approach is lacking. There is a need for a processor that maintains cryptographic strength while significantly reducing computational latency. This research aims to bridge these gaps by designing a low-resource and low-latency 163-bit ECC processor that implements a hybrid Karatsuba multiplier and QuadItoh-Tsuji inversion for enhanced efficiency. It balances low latency, high security, and resource efficiency for IoT applications. Provides comparative analysis against existing ECC implementations to validate its performance. The processor is synthesized with PlanAhead software and implemented on several Virtex FPGAs. The most significant achievement of the design is its ability to minimize the latency to 991 cycles. In comparison to other designs, the implemented design is the most suited for Virtex-4 and 5. It is the smallest on Virtex-4 compared to other designs in the literature. In comparison to existing designs, the implemented approach saves 40-50% of resources on Virtex-4 and Virtex-7 implementations. Although the design's maximum frequency is lower than other designs, its area-time product yields good results. It also shows satisfactory values for the areatime product compared to previous designs.