A Random Forest-Based Approach for Yield Estimation in VLSI Circuit Design

Abstract

Yield estimation in Very Large Scale Integration (VLSI) circuit design is a critical phase of ensuring the reliability and profitability of semiconductor manufacturing. Conventionally, yield estimation is achieved through Monte Carlo (MC) simulations, a computational method that relies on repeated random sampling and simulation to obtain numerical results. A major drawback of this method is its high computational cost, often requiring a large number of simulations for accurate results. This work presents a novel approach for estimating circuit yield by utilizing the capabilities of random forest algorithms, a powerful machine learning technique, to provide a more accurate and efficient solution. By significantly reducing the computational burden associated with simulating numerous circuit samples, this approach offers a viable alternative to the traditional MC method. Experimental results demonstrate that the proposed approach can significantly accelerate yield estimation while incurring a reasonable loss in accuracy. © 2025 Institute of Electrical Engineers of Japan and Wiley Periodicals LLC.