A sleek lock-free hash map in an ERA of safe memory reclamation methods

IF 2.1 4区 计算机科学 Q2 COMPUTER SCIENCE, THEORY & METHODS
Parallel Computing Pub Date : 2025-11-01 Epub Date: 2025-10-29 DOI:10.1016/j.parco.2025.103162
Pedro Moreno , Miguel Areias , Ricardo Rocha
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引用次数: 0

Abstract

Lock-free data structures have become increasingly significant due to their algorithmic advantages in multi-core cache-based architectures. Safe Memory Reclamation (SMR) is a technique used in concurrent programming to ensure that memory can be safely reclaimed without causing data corruption, dangling pointers, or access to freed memory. The ERA theorem states that any SMR method for concurrent data structures can only provide at most two of the three main desirable properties: Ease of use, Robustness, and Applicability. This fundamental trade-off influences the design of efficient lock-free data structures at an early stage. This work redesigns a previous lock-free hash map to fully exploit the properties of the ERA theorem and to leverage the characteristics of multi-core cache-based architectures by minimizing the number of cache misses, which are a significant bottleneck in multi-core environments. Experimental results show that our design outperforms the previous design, which was already quite competitive when compared against the Concurrent Hash Map design of the Intel’s TBB library.
一个光滑的无锁哈希映射在一个安全的内存回收方法的年代
无锁数据结构由于其在基于多核缓存的体系结构中的算法优势而变得越来越重要。安全内存回收(SMR)是并发编程中使用的一种技术,用于确保可以安全地回收内存,而不会导致数据损坏、悬空指针或访问已释放的内存。ERA定理指出,任何用于并发数据结构的SMR方法最多只能提供三个主要理想属性中的两个:易用性、健壮性和适用性。这种基本的权衡在早期阶段就影响了高效无锁数据结构的设计。这项工作重新设计了以前的无锁哈希映射,以充分利用ERA定理的属性,并通过最小化缓存缺失的数量来利用基于多核缓存的架构的特征,这是多核环境中的一个重要瓶颈。实验结果表明,我们的设计优于之前的设计,与Intel的TBB库的Concurrent Hash Map设计相比,我们的设计已经很有竞争力了。
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来源期刊
Parallel Computing
Parallel Computing 工程技术-计算机:理论方法
CiteScore
3.50
自引率
7.10%
发文量
49
审稿时长
4.5 months
期刊介绍: Parallel Computing is an international journal presenting the practical use of parallel computer systems, including high performance architecture, system software, programming systems and tools, and applications. Within this context the journal covers all aspects of high-end parallel computing from single homogeneous or heterogenous computing nodes to large-scale multi-node systems. Parallel Computing features original research work and review articles as well as novel or illustrative accounts of application experience with (and techniques for) the use of parallel computers. We also welcome studies reproducing prior publications that either confirm or disprove prior published results. Particular technical areas of interest include, but are not limited to: -System software for parallel computer systems including programming languages (new languages as well as compilation techniques), operating systems (including middleware), and resource management (scheduling and load-balancing). -Enabling software including debuggers, performance tools, and system and numeric libraries. -General hardware (architecture) concepts, new technologies enabling the realization of such new concepts, and details of commercially available systems -Software engineering and productivity as it relates to parallel computing -Applications (including scientific computing, deep learning, machine learning) or tool case studies demonstrating novel ways to achieve parallelism -Performance measurement results on state-of-the-art systems -Approaches to effectively utilize large-scale parallel computing including new algorithms or algorithm analysis with demonstrated relevance to real applications using existing or next generation parallel computer architectures. -Parallel I/O systems both hardware and software -Networking technology for support of high-speed computing demonstrating the impact of high-speed computation on parallel applications
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