Energy-efficient ternary in-memory computing architecture for versatile health monitoring in wearable devices

Abstract

The rising prevalence of severe health conditions has increased the demand for e-healthcare solutions, particularly wearable devices for continuous monitoring and early detection. Nevertheless, the limited battery life and the substantial computational demands necessary for disease diagnosis pose significant challenges for these devices when using conventional computing systems. This paper presents a novel ternary memory architecture supporting in-memory computing (IMC) to address these challenges. The design features an advanced 1-transistor 1-RRAM (1T1R) ternary memory basic cell, which reduces storage requirements and enhances latency and power efficiency. This architecture also supports ternary logic operations within memory, utilizing a ternary polymorphic design to efficiently perform ternary operations, including basic logic functions, addition, and multiplication. This functionality enables the development of low-power, energy-efficient ternary neural networks for early disease detection and continuous monitoring. The post-layout simulations performed using the Cadence Virtuoso tool and the well-established TSMC 40 nm CMOS technology indicate that the proposed design achieves a 91 % reduction in storage energy consumption compared to existing alternatives. An in-memory implementation of the ternary full adder and multiplier results in an energy savings of 90.3 % compared to previous designs. Furthermore, the proposed ternary architecture is applied to skin cancer diagnosis in wearable devices, using the ternary IRV2 neural network for classification with the HAM10000 dataset. The ternary implementation yields a 97 % power saving compared to full-precision classification while maintaining an accuracy of 88 %.