{"title":"A low-power switching technique for SAR ADCs achieving energy efficient transitions at the input and reference voltage sources","authors":"Mehdi Sotoudeh, Mehdi Habibi","doi":"10.1016/j.compeleceng.2025.110728","DOIUrl":null,"url":null,"abstract":"<div><div>This study presents an alternative approach to capacitor switching aimed at lowering switching energy in successive approximation register analog-to-digital converters (SAR ADCs). This approach eliminates energy consumption from the input voltage by establishing a direct connection to the comparator’s positive terminal. To mitigate offset drawbacks, a low-power offset-cancellation comparator is employed. Furthermore, by isolating all capacitors connected to the comparator’s negative terminal during the switching of reference voltages, the energy overhead introduced by toggling the reference voltages is also ideally reduced to zero. This achieves a theoretical 100% reduction in switching energy compared to conventional SAR ADC methods under idealized assumptions. In practice, non-ideal factors such as parasitic capacitance, charge injection, comparator dynamic power, and control logic overhead contribute to residual energy consumption. This energy reduction is achieved while maintaining a low complexity in the control block. Additionally, this architecture employs only 25% of the capacitors required in traditional design, leading to substantial hardware savings. The suggested 8-bit SAR ADC was simulated in a 65 nm CMOS process with a 1.2 V power supply, 0.9 V reference voltage, and an operating sampling rate of 1 MS/s. As observed in the simulation data, the effective number of bits, power dissipation, and figure of merit are determined to be 6.9 bits, 1.91 µW, and 15.99 fJ/conversion-step, respectively. To evaluate the converter's efficiency, Monte Carlo, corner, and temperature simulations were conducted, demonstrating satisfactory performance.</div></div>","PeriodicalId":50630,"journal":{"name":"Computers & Electrical Engineering","volume":"128 ","pages":"Article 110728"},"PeriodicalIF":4.9000,"publicationDate":"2025-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Computers & Electrical Engineering","FirstCategoryId":"94","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0045790625006718","RegionNum":3,"RegionCategory":"计算机科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q1","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 0
Abstract
This study presents an alternative approach to capacitor switching aimed at lowering switching energy in successive approximation register analog-to-digital converters (SAR ADCs). This approach eliminates energy consumption from the input voltage by establishing a direct connection to the comparator’s positive terminal. To mitigate offset drawbacks, a low-power offset-cancellation comparator is employed. Furthermore, by isolating all capacitors connected to the comparator’s negative terminal during the switching of reference voltages, the energy overhead introduced by toggling the reference voltages is also ideally reduced to zero. This achieves a theoretical 100% reduction in switching energy compared to conventional SAR ADC methods under idealized assumptions. In practice, non-ideal factors such as parasitic capacitance, charge injection, comparator dynamic power, and control logic overhead contribute to residual energy consumption. This energy reduction is achieved while maintaining a low complexity in the control block. Additionally, this architecture employs only 25% of the capacitors required in traditional design, leading to substantial hardware savings. The suggested 8-bit SAR ADC was simulated in a 65 nm CMOS process with a 1.2 V power supply, 0.9 V reference voltage, and an operating sampling rate of 1 MS/s. As observed in the simulation data, the effective number of bits, power dissipation, and figure of merit are determined to be 6.9 bits, 1.91 µW, and 15.99 fJ/conversion-step, respectively. To evaluate the converter's efficiency, Monte Carlo, corner, and temperature simulations were conducted, demonstrating satisfactory performance.
期刊介绍:
The impact of computers has nowhere been more revolutionary than in electrical engineering. The design, analysis, and operation of electrical and electronic systems are now dominated by computers, a transformation that has been motivated by the natural ease of interface between computers and electrical systems, and the promise of spectacular improvements in speed and efficiency.
Published since 1973, Computers & Electrical Engineering provides rapid publication of topical research into the integration of computer technology and computational techniques with electrical and electronic systems. The journal publishes papers featuring novel implementations of computers and computational techniques in areas like signal and image processing, high-performance computing, parallel processing, and communications. Special attention will be paid to papers describing innovative architectures, algorithms, and software tools.