A low-power switching technique for SAR ADCs achieving energy efficient transitions at the input and reference voltage sources

IF 4.9 3区 计算机科学 Q1 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
Mehdi Sotoudeh, Mehdi Habibi
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引用次数: 0

Abstract

This study presents an alternative approach to capacitor switching aimed at lowering switching energy in successive approximation register analog-to-digital converters (SAR ADCs). This approach eliminates energy consumption from the input voltage by establishing a direct connection to the comparator’s positive terminal. To mitigate offset drawbacks, a low-power offset-cancellation comparator is employed. Furthermore, by isolating all capacitors connected to the comparator’s negative terminal during the switching of reference voltages, the energy overhead introduced by toggling the reference voltages is also ideally reduced to zero. This achieves a theoretical 100% reduction in switching energy compared to conventional SAR ADC methods under idealized assumptions. In practice, non-ideal factors such as parasitic capacitance, charge injection, comparator dynamic power, and control logic overhead contribute to residual energy consumption. This energy reduction is achieved while maintaining a low complexity in the control block. Additionally, this architecture employs only 25% of the capacitors required in traditional design, leading to substantial hardware savings. The suggested 8-bit SAR ADC was simulated in a 65 nm CMOS process with a 1.2 V power supply, 0.9 V reference voltage, and an operating sampling rate of 1 MS/s. As observed in the simulation data, the effective number of bits, power dissipation, and figure of merit are determined to be 6.9 bits, 1.91 µW, and 15.99 fJ/conversion-step, respectively. To evaluate the converter's efficiency, Monte Carlo, corner, and temperature simulations were conducted, demonstrating satisfactory performance.
一种用于SAR adc的低功耗开关技术,可在输入和参考电压源处实现高能效转换
本研究提出了一种替代电容开关的方法,旨在降低连续逼近寄存器模数转换器(SAR adc)的开关能量。这种方法通过建立与比较器正极的直接连接,消除了输入电压的能量消耗。为了减轻偏移的缺点,采用了低功率偏移抵消比较器。此外,在基准电压切换期间,通过隔离连接到比较器负极端的所有电容器,通过切换基准电压引入的能量开销也理想地降低到零。在理想假设下,与传统的SAR ADC方法相比,理论上实现了100%的开关能量降低。在实际中,寄生电容、电荷注入、比较器动态功率和控制逻辑开销等非理想因素会导致剩余能量消耗。在控制块保持低复杂度的同时实现了这种能量减少。此外,该架构仅使用传统设计所需电容器的25%,从而节省了大量硬件。在1.2 V电源、0.9 V参考电压、1 MS/s工作采样率的65 nm CMOS工艺条件下,对所设计的8位SAR ADC进行了仿真。从仿真数据中可以看出,有效比特数、功耗和优值分别为6.9比特、1.91µW和15.99 fJ/转换步长。为了评估变换器的效率,进行了蒙特卡罗、角落和温度模拟,证明了令人满意的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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来源期刊
Computers & Electrical Engineering
Computers & Electrical Engineering 工程技术-工程:电子与电气
CiteScore
9.20
自引率
7.00%
发文量
661
审稿时长
47 days
期刊介绍: The impact of computers has nowhere been more revolutionary than in electrical engineering. The design, analysis, and operation of electrical and electronic systems are now dominated by computers, a transformation that has been motivated by the natural ease of interface between computers and electrical systems, and the promise of spectacular improvements in speed and efficiency. Published since 1973, Computers & Electrical Engineering provides rapid publication of topical research into the integration of computer technology and computational techniques with electrical and electronic systems. The journal publishes papers featuring novel implementations of computers and computational techniques in areas like signal and image processing, high-performance computing, parallel processing, and communications. Special attention will be paid to papers describing innovative architectures, algorithms, and software tools.
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