Efficient and scalable designs for ternary quantum reversible multiplexer and demultiplexer systems

Abstract

In recent years, ternary reversible logic has become a promising paradigm for advancing low-power, high-performance quantum digital systems that preserve information and are energy efficient. This paper focuses on two primary objectives: first, the efficient realization of ternary reversible \(3 \times 1\) multiplexers and \(1 \times 3\) demultiplexers using quantum gates, specifically 1-qutrit Shift and 3-qutrit Controlled Feynman gates, and second, the design of generalized \(n \times 1\) multiplexers and \(1 \times n\) demultiplexers. The proposed \(9 \times 1\) multiplexer we propose in this study has demonstrated notable improvements in terms of quantum cost (20%), depth (18%), number of constant inputs (60%), and garbage outputs (30%), while the proposed \(1 \times 9\) demultiplexer shows a 20% reduction in quantum cost, a 18% reduction in depth, a 33% reduction in constant inputs, and a 50% reduction in garbage outputs, compared to the most efficient existing designs. These optimizations represent an important step forward in the development of more efficient ternary and quantum reversible logic circuits, advancing the scalability of quantum systems.